Publications on the project |
047 Nanocluster NVM Cells Metrology: Window formation, Relaxation and Charge Retention Measurements |
Authors: | V. A. Ievtukh, A. N. Nazarov, V. I. Turchanikov and V. S. Lysenko | |
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Edition: | Advanced Materials Research Vols. 718-720, pp 1118-1123 | | | 2013,
,English |
047 Charge trapping processes at memory window formation in single- and double nanocrystal layered NVMs |
Authors: | V. Ievtukh, A. Nazarov, V. Turchanikov, V. Lysenko, A. Nassiopoulou | |
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Edition: | Microelectronic engineering, Vol. 109, pp 5-9 | | | 2013,
,English |
047 V.I. Turchanikov, V.A. Ievtukh, A.N. Nazarov Charge trapping and retention in nanocrystal Non Volatile Memory structure |
Authors: | V.I. Turchanikov, V.A. Ievtukh, A.N. Nazarov | |
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Edition: | Joint 6th SemOI Workshop & 1st Ukrainian-French SOI Seminar | | | 2010,
,English |
047 Charge relaxation and charge retention in single- and double-layer nanocrystal MOS non-volatile memory cells using capacitance measurements |
Authors: | V. Ievtukh, A. Nazarov et al | |
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Edition: | 17th Workshop on Dielectrics in Microelectronics | | | 2012,
,English |
047 Nanocrystal NVM Cells Electrical Parameters Measurement Specificity |
Authors: | V. Turchanikov, V. Ievtukh, A. Nazarov, V. Lysenko | |
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Edition: | IEEE R8 International conference on computer as a tool, EUROCON2011,A28P3-208 | | | 2011,
,English |
047 Single- and double layered Si nanocrystal structures in SiO2 for non-volatile memory devices |
Authors: | Ievtukh V., Nazarov A., Lysenko V. | |
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Edition: | 2nd International research and practice conference «Nanotechnology and Nanomaterials» | | | ,
, |
047 Nanocrystal nonvolatile memory devices metrology by method of capacitance diagnostics |
Authors: | V.Ievtukh, A. Nazarov, V. Lysenko | |
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Edition: | Nanoscale systems and nanomaterials: status and prospects of researtch developement in Ukraine 2014 | | | 2014,
,Russian |
The events in the framework of the project |
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047 3. Diagnostics of nanostructures Purpose:The electric diagnostic methods development for nonvolatile memory devices with floating gate made of silicon nanoinclusions and nanostructures. Developement of specialized diagnostic equipment and software dedicated for electro research. The diagnostics algorithms developement, software testing and hardware complex developement for capacitor-type memory cells with nanoinclusions and transistor structures. Expected results:Issue of new types of products: methods, theories Stage 1:Modification of existing diagnostic systems, development and production of sub-elements Stage 2:Development of diagnostic methods for programming/erasing window width determination, development of algorithms, stress testing. Stage 3:Development of methods for determining the stored charge relaxation characteristics during cell reprogramming; algorithms development; stress testing. Stage 4:Development diagnostic methods of data storage properties of memory cells in time deflection; algorithms developement; stress testing. Stage 5:The method development for rapid diagnostics of memory cell programming/erasing window width, determination the charge relaxation characteristics during reprogramming at elevated temperatures.
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